Astera Labs and the connectivity tax on every AI rack

There's a story Jensen Huang likes to tell about the early days of Nvidia, when nobody believed graphics chips would matter outside of video games. He tells it because it makes a clean arc, garage company to four-trillion-dollar colossus, and because it lets the audience pattern-match for the next one. Everyone in the room is thinking the same thing while he talks. Where is the next Nvidia hiding?

The honest answer is that it probably isn't hiding in another GPU company. The compute layer has been picked over, priced up, and worshipped to within an inch of its life. AMD, Broadcom, Marvell, every custom silicon shop with a hyperscaler logo on the slide deck, all of it is now consensus. If you want to find the asymmetric trade inside AI hardware in 2026, you have to look at what sits between the chips, not the chips themselves.

Most investors still haven't internalized what modern AI training actually requires. A single Nvidia GB200 NVL72 rack is, electrically, one computer. Seventy-two Blackwell GPUs wired together as if they were cores on a single die. The cables, retimers, switches and active electrical interconnects that bind them are not accessories. They are the computer. When you read that an NVL72 rack does 1.4 exaflops of FP4, that number is a fiction unless every signal between every GPU arrives clean, on time, and with bit-perfect fidelity. Lose a few picoseconds of timing budget on a 224 gigabit-per-second SerDes lane and the whole rack throttles. Lose a retimer and you lose a node. Lose a node and a 30-day training run goes sideways.

This is why hyperscaler capex is shifting in a way the headlines miss. Microsoft, Meta, Amazon and Google are still buying GPUs hand over fist, but the second derivative, the part growing fastest inside each rack, is connectivity. Active electrical cables. PCIe and CXL retimers. Smart cable modules. Optical DSPs for the rack-to-rack hops. The bill of materials for an AI server in 2026 looks nothing like a 2022 server. Networking and interconnect now eat 15 to 20 percent of the rack cost, up from low single digits a few years ago. On a trillion-dollar AI infrastructure spend cycle, that delta is its own industry.

And it's a tougher industry to enter than people realize. SerDes design is one of the genuinely hard problems in semiconductors. You are pushing analog signals at frequencies where the copper itself behaves like an antenna, the PCB substrate matters, the connector geometry matters, the temperature inside the rack matters. You can't fix a bad SerDes with a software patch. The companies that have spent a decade learning how to keep those signals alive at 100, 200, now 400 gigabits per second per lane have a moat that doesn't show up in any 10-K. It shows up in the fact that when a hyperscaler designs a new AI rack, they call the same two or three suppliers every time.

Now trace the chain reaction. Nvidia's roadmap calls for Rubin in late 2026 and Rubin Ultra in 2027, with NVLink bandwidth roughly doubling each generation. Doubling NVLink bandwidth doesn't mean twice as many connectors. It means the existing connectors get replaced by faster, more complex, more expensive ones, and the count goes up too because rack sizes are scaling from 72 GPUs to 144 to 576. The unit economics for the connectivity vendors get better with every generation, not worse, because the silicon content per port keeps rising. This is the opposite of the commodity dynamic that crushed margins in PC components for thirty years.

Meanwhile, the custom ASIC wave (Google TPU v7, AWS Trainium 3, Meta MTIA v3, Microsoft Maia 2) creates a second tailwind. Every custom chip needs the same interconnect IP that Nvidia needs, and the hyperscalers don't want to design SerDes in-house because the failure mode is too painful. They license it, or they buy the retimer chips outright. The connectivity vendors get paid whether the AI workload runs on Nvidia, AMD, or somebody's bespoke silicon. They are agnostic to the GPU war.

Which brings us to the company at the center of this. Founded in 2017 in San Jose by a small team of analog engineers who had spent careers at Texas Instruments and Inphi, it went public in March 2024 to genuine fanfare and then, as is the way of these things, drifted out of the daily headlines as the market moved on to the next shiny GPU launch. The company makes PCIe and CXL retimers, smart cable modules, CXL memory controllers, and the fabric switches that tie AI server racks together. Its customers are every hyperscaler you can name. Its products are designed into the reference architectures that the rest of the industry copies.